FPGA HFT · UC San Diego · 2026

ITCH 5.0
Parser &
Limit Order Book

A hardware NASDAQ market data decoder in pure Verilog, targeting the Xilinx Alveo U55C. Processes raw exchange bytes in silicon — no CPU, no OS — and outputs live best bid/ask prices in under 840 nanoseconds.

View on GitHub See the architecture ↓
<840 nanosecond latency
100 MHz clock speed
8.71 ns timing slack · U55C
<0.01% chip utilization
01 — Architecture

How it works

INPUT
NASDAQ
100G raw feed
MODULE 01
AXI Adapter
512-bit → 8-bit
tkeep handled
MODULE 02
ITCH Decoder
Add / Execute
Cancel / Delete
MODULE 03
Order Book
Best bid/ask
hardware regs
OUTPUT
Signal
best_bid [31:0]
best_ask [31:0]
MODULE 01
AXI-Stream Adapter
The 100G CMAC delivers data in 512-bit chunks. This module deserializes it to a byte-serial stream and handles the tkeep signal to skip padding bytes on partial Ethernet frames.
axis_512_to_8_adapter.v
MODULE 02
ITCH 5.0 Decoder
A finite state machine reading one byte per clock cycle at 100 MHz. Identifies message type from the first byte, then extracts price, shares, and side from each of the four ITCH 5.0 message types.
itch_decoder.v
MODULE 03
Limit Order Book
Updates best bid and ask price in hardware registers after every decoded message. Zero memory lookup latency — outputs are always live and current.
order_book.v
02 — Results

Simulation & synthesis

Vivado xsim — full ITCH pipeline
$ xsim itch_snap --runall
Time resolution is 1 ps · run -all
End of valid hex data reached at index 720
$finish called at time : 7520 ns
exit
 
✓ PASS — 720 bytes · AAPL / SPY / MSFT · Add, Execute, Cancel, Delete · 0 errors
Timing slack (WNS)
+8.71ns
Target: 10 ns (100 MHz). 87% margin — design could run at ~700 MHz. Synthesized on Alveo U55C xcu55c-fsvh2892-2L-e.
CLB LUTs used
11/1.3M
Less than 0.01% of available logic resources. 0 BRAM, 0 DSPs. Pure combinational logic — extremely lean.
Flip-flops
10/2.6M
Minimal state registers. The FSM compresses down to just the essential state bits after Vivado optimization.
Synthesis status
0 errors
0 critical warnings
Vivado 2023.2 · xcu55c-fsvh2892-2L-e · Speed grade -2L
03 — Context

Where this fits

This module was built as part of a 6-person end-to-end HFT pipeline at UC San Diego's Triton Quantitative Trading club. The full system targets two Xilinx Alveo U55C cards on the Nautilus NRP Kubernetes cluster, connected via QSFP+ loopback.

My responsibility was the core decode engine — the step between raw network bytes and actionable trading signals. Beyond the Verilog modules, I also configured the ESnet SmartNIC build framework, debugged a Vivado containerization crash in Kubernetes, and built the full Vitis RTL kernel packaging pipeline.

The design was validated in Vivado simulation against real Databento NASDAQ ITCH 5.0 market data and synthesized successfully on the Alveo U55C target hardware.

  • 01 Databento feed ingestion + PCIe bitstreamer
  • 02 100G Ethernet + AXI-Stream transport
  • 03 MAC / IPv4 / UDP header stripping
  • 04 MoldUDP64 envelope parser
  • 05 ITCH 5.0 decoder + Limit Order Book ← this repo
  • 06 Feature engine (momentum, vol-imbalance, etc.)
  • 07 MLP 6-8-1 strategy engine